Modem semiconductor integrated circuits, usually formed in silicon substrates or wafers, include not only the active semiconductor devices but also several metallization levels formed over the silicon substrate to provide the complex electrical connections required for integrated circuits incorporating tens or hundreds of millions of discrete semiconductor devices. Regularly arranged memory circuits can be designed with only three metallization levels, but advanced logic devices such as microprocessors may require five or more levels.
Each metallization level requires a dielectric layer of, for example, silicon dioxide separating two levels of horizontal lines of, for example, aluminum extending horizontally across the integrated circuit. Via holes are etched through the dielectric layer and filled with a conductor, most usually aluminum, to connect aluminum lines on different levels. The first metallization level has a dielectric layer formed directly over the silicon substrate, and contact holes filled with a conductor, which may be tungsten, connect the first-level aluminum lines with the active semiconductor devices.
Although there has been much recent interest in copper metallization and a dual-damascene metallization structure which does not require etching of copper, it is believed that the more conventional aluminum metallization lines formed by etching aluminum will continue to be effective even as feature sizes are reduced to 0.13 μm and below.
The formation of a typical metallization structure is illustrated in the sectioned orthographic view of FIG. 1, which emphasizes the fact that the horizontally extending metallization lines are often aggregated into buses of multiple parallel lines 10, 12 having a minimum gap 14 between them. This figure does not include metallized vias penetrating an oxide layer. The lines 10, 12 may be formed with horizontal features sizes of 0.25 μm or less with a gap 14 between them of approximately the same size. For such small feature sizes, special care must be exercised because the small horizontal feature sizes are being reduced while the vertical dimensions are being maintained nearly constant at about 0.7 μm or somewhat above. A generally planar stack structure is first deposited on an underlying dielectric layer 16 separating this metallization level from the underlying metallization level or the silicon substrate. Unillustrated via holes may penetrate the dielectric layer 16 to contact conductive structure in the underlying layer to the aluminum lines 10, 12. Until recently, the dielectric layer 16 has typically been silica, of the approximate composition SiO2, and other silicate glasses. However, there has been much recent interest in low-k dielectrics, that is, having a lower dielectric constant than silica. One example is fluorosilicate glass (FSG). Other low-k dielectrics include silicon-based oxides and carbon-based polymers.
The stack structure comprises from the bottom a thin barrier layer 18, typically of Ti/TiN, an aluminum layer 20, a lower anti-reflective coating (ARC) layer 22, typically of TiN, and an upper ARC layer 24, either of an organic ARC material or a inorganic one, such as silicon oxynitride (SiON). In a typical via process, the barrier layer 18 is conformally coated onto the sides of the via as well as to the top of the dielectric layer 16 and the aluminum layer 20 fills the remainder of the via and extends above the top of the via to provide aluminum for horizontal interconnects. The remaining layers 22, 24 are deposited over the planar top of the aluminum layer 20.
A SiON ARC layer is often referred to as dielectric ARC or DARC. An alternative upper ARC layer 24 is an organic ARC material, generically called BARC, which is a carbon-based polymer. The aluminum layer 20 is typically formed of an aluminum alloy of aluminum and less than 10 wt % of an alloying element, for example, 0.5 to 2% of copper. Silicon is another alloying element of less than 10% alloying fraction. In the barrier layer 18, the TiN is acting as the actual barrier. The somewhat optional Ti acts as a glue layer to the underlying oxide. Typical thicknesses for the layers are presented in TABLE 1.
TABLE 1Thickness(nm)SiON ARC30-60Organic ARC 60-150TiN ARC 25-150Al-M1300-500Al-M2400-800TiN Barrier 25-100Ti Glue10-50The thickness of the aluminum typically increases from the lowest level M1 of metallization to increasingly thicker layers in the upper levels, such as the second metal level M2.
A photoresist layer 26 is deposited over the planar stack structure and photographically patterned into a photoresist mask. Thereafter, dry plasma etching is used to etch through the ARC layers 24, 22, the aluminum layer 20, and the Ti/TiN barrier layer 18 according to the pattern of the photomask. It is preferred that the etching extend partially into the oxide layer 16 in what is referred to as an over etch producing a recess 28 in the oxide layer 16. An exemplary depth of the oxide recess is 50 nm. The over etch avoids two problems which would otherwise tend to electrically short together the adjacent aluminum lines 10, 12. The Ti/TiN barrier 18 has a small but finite electrically conductivity, but the etching process has some window of processing parameters. To guarantee that the slightly conductive Ti/TiN barrier 18 is not continuous between the two lines 10, 12 but is interrupted by the gap 14, the recess 28 produced by the over etch assures that the Ti/TiN barrier 18 is removed in the gap 14. The recess 28 is also effective in isolating any conductive metallic residues that may form at the bottom of the gap 14 from contacting the partially conductive Ti/TiN barrier layers 18 of the two aluminum lines 10, 12.
Deep ultraviolet (DUV) radiation is used to pattern the photoresist 26 because of the small features being defined. The two ARC layers 22, 24 are needed to maintain the resolution of the patterning radiation. Furthermore, the thickness of the DUV photoresist 26 needs to be limited if the patterning radiation is to maintain focus through the photoresist thickness. The limited photoresist thickness imposes a strict requirement on the selectivity relative to photoresist of the etching of the other layers. That is, the entire etch process requires a high photoresist selectivity. Inevitably, a significant amount of the photoresist is etched. Photoresist involves complex photochemistry but for etching purposes it can be characterized as a carbon-based polymer, in particular, nearly a polyethylene composition of —(CH2)n—. The etched polymer is likely to coat the chamber walls. Although a polyethylene chamber coating is relatively dense and robust, if it builds up excessively, it will flake off creating a substantial particle problem. Accordingly, it is common practice to wet clean the chamber after a few hundred to a few thousand wafers, a process that requires operator time and reduces system uptime. An important metric for the commercial feasibility is the mean number of wafers between chamber clean (MWBC), a number which should be minimized. Chen et al. in U.S. Pat. No. 5,356,478 has suggested occasional but long chamber dry cleaning with a chlorine and oxygen plasma.
Plasma etching of aluminum is usually performed using chlorine gas (Cl2) as the primary etching gas because of its high aluminum etching rate. Boron trichloride (BCl3) is often used in combination with chlorine gas. Although not as fast at etching aluminum, it provides some passivation, which will be explained immediately below. A chlorine-containing etching gas reacts with aluminum to form aluminum trichloride (AlCl3), which is volatile and is mostly exhausted from the etching chamber. A fluorocarbon such as CF4 is sometimes added to the chlorine-based etching gas as a passivation gas to protect the photoresist and thus provide high photoresist selectivity and to coat the sidewalls and thus provide a good vertical profile in the aluminum. The benefits arise because the fluorocarbon under the proper conditions deposits a protective carbonaceous polymeric coating on the photoresist and on the aluminum sidewalls that is resistant to etching. However, fluorine radicals produced by the plasma interact with the aluminum being etched to form aluminum trifluoride (AlF3), which is not only non-volatile but also forms a very hard material and which tends to deposit on the wafer and on the chamber walls. Even if aluminum is not being etched in a particular step, a substantial amount of AlCl3 is nonetheless present in the chamber, often produced in a previous step and entrained in a polymeric residue built up on the chamber walls. Fluorine radicals created in a plasma of a fluorine-containing gas will react with AlCl3 to produce AlF3. The AlF3 material may immediately form hard particles or it may deposit onto the chamber wall. Since carbonaceous polymer is also being coated on the chamber wall, the combination of the soft organic polymer and the hard inorganic metal fluoride does not bond together well and is not densified. The combination is unstable and readily flakes. In either case, the non-volatile AlF3 or possibly small polymer particles are likely to fall on the wafer being etched. Even a single small particle falling on a small feature, such as the inter-line gap 14, is likely to cause the entire integrated circuit to fail.
To minimize the chamber flaking problem, it is typical to periodically clean the chamber wall. However, there is no known plasma chemistry which can etch AlF3, most probably because the large difference in electronegativity of the two elements produces a very strong chemical bond. Instead, wet cleaning is typically used. Wet cleaning interrupts production, and wet cleaning AlF3 is not completely effective anyway because AlF3 is such a tough insoluble material. The wet cleaning cycle when AlF3 is being produced may be as little as a few hundred wafers, clearly a commercially disadvantageous number for MWBC. The use of fluorocarbon etchants is also likely to produce aluminum fluoride when the chamber wall or other chamber parts are composed of anodized aluminum, that is, alumina, the preferred material because of its low cost and easy machinability. Alumina is readily etched by a fluorine plasma, which further introduces a problem with chamber lifetime.
Nitrogen gas or other nitrogen-containing compounds have also been suggested as passivating gases for achieving vertical profiles in aluminum etching. However, such a nitrogen passivating gas has been observed to deposit an ammonium salt on the chamber wall. Although such a salt is susceptible to etching by an oxygen and chlorine plasma, the cleaning rate is very slow.
Nawata has proposed in U.S. Pat. No. 5,618,398 that a substantial fraction of CH4 be added to a Cl2/BCl3 gas plasma for etching aluminum and that C2H4 is one of several hydrocarbons that can substituted for CH4.
The etching of the upper ARC layer 24 also presents problem because it has typically used a fluorine-containing gas. The typical etching recipe for DARC or SiON is combination of Cl2/BCl3/Ar/CHF3/CF4, often Cl2/CHF3 or Cl2/CF4 or Cl2/BCl3 with the addition of fluorine-containing gas. A fluorine-containing etching gas containing fluorocarbons and hydrofluorocarbons has the advantage in etching SiON, which is very similar to SiO2, that it generates the protective polymer over the photoresist and other non-oxide materials and also deposits a polymer on the sidewall which promotes a vertical etch. Similarly, the recipe for BARC is typically Cl2/Ar/CHF3/CF4. However, the presence of the fluorine-containing fluorocarbon, hydrofluorocarbon, or other fluorine-containing gas will again produce AlF3 with the same deleterious results.
For all these reasons, it is desirable to provide an integrated process for plasma etching aluminum lines in which none of the critical steps of the process uses fluorine. It is also desirable that all the steps provide a high selectivity to photoresist and aluminum sidewall passivation while nonetheless achieving an acceptable etching rate of the material intended to be etched, especially the aluminum.
It is also desirable that the etching steps forming the integrated process be performed in a single plasma etch reactor.
It is further desirable that the process involves little or no wet cleaning of the chamber. If occasional wet cleaning is required, is should be infrequent so that the MWBC value should be large